From fd661b8ae4bb55e357e46103148bea6bc36c1dfa Mon Sep 17 00:00:00 2001
From: nalydmerc <nalydmerc@gmail.com>
Date: Thu, 3 Apr 2025 23:21:05 -0400
Subject: [PATCH] MCU LED Now turns on!

---
 Cargo.toml  |  5 ++++-
 src/main.rs | 10 ++++++++++
 2 files changed, 14 insertions(+), 1 deletion(-)

diff --git a/Cargo.toml b/Cargo.toml
index 68bfba2..50681a4 100644
--- a/Cargo.toml
+++ b/Cargo.toml
@@ -10,7 +10,10 @@ cortex-m = { version = "0.7.6", features = ["critical-section-single-core"] }
 cortex-m-rt = "0.7"
 cortex-m-semihosting = "0.5"
 panic-halt = "1.0.0"
-stm32f1 = "0.15.1"
+
+[dependencies.stm32f1]
+version = "0.15.1"
+features = ["stm32f103"]
 
 # Uncomment for the panic example.
 # panic-itm = "0.4.1"
diff --git a/src/main.rs b/src/main.rs
index b685a8c..b8d00da 100644
--- a/src/main.rs
+++ b/src/main.rs
@@ -10,12 +10,22 @@ use panic_halt as _; // you can put a breakpoint on `rust_begin_unwind` to catch
 use cortex_m::asm;
 use cortex_m_rt::entry;
 use cortex_m_semihosting::hprintln;
+use stm32f1::stm32f103;
 
 #[entry]
 fn main() -> ! {
     asm::nop(); // To not have main optimize to abort in release mode, remove when you add code
     hprintln!("Hello, world!");
 
+    let peripherals = stm32f103::Peripherals::take().unwrap();
+
+    // Enable clock for GPIOA by setting IOPAEN in RCC APB2ENR
+    peripherals.RCC.apb2enr.modify(|_, w| w.iopaen().set_bit());
+
+    peripherals.GPIOA.crl.modify(|_, w| w.mode3().output());
+    peripherals.GPIOA.crl.modify(|_, w| w.cnf3().push_pull());
+    peripherals.GPIOA.odr.modify(|_, w| w.odr3().high());
+
     loop {
         // your code goes here
         asm::nop();